The present invention relates to an oscillation circuit and more particularly to an oscillation circuit with an improved oscillation frequency characteristic.
A pulse generating circuit is one of the most important circuits in electronic circuitry, and is used, for example, as a circuit drive source. Of the pulse generating circuits proposed, a CR oscillation circuit, which is simple in construction and allows high density integration, has dominantly been used. The CR oscillator (referred to as an oscillation circuit for brevity) generates a pulse signal at a frequency according to the time constant of the capacitor and the resistor contained in the circuit. FIG. 1 shows a prior oscillation circuit. In the figure, the oscillation circuit has a power transmission gate circuit TrN (referred to as a transmission gate circuit) connected between the power source (V.sub.DD -V.sub.SS). The transmission gate circuit is formed of an N-channel MOS transistor, for example. The power source is supplied through the transmission gate circuit TrN to a parallel CR circuit 10 including a capacitor Cx and a resistor Rx. The voltage Vi generated according to the time constant of the capacitor Cx and the resistor Rx in the CR circuit 10 is supplied to a Schmitt trigger gate circuit 12. The gate circuit 12 produces a pulse output signal Vout at a predetermined frequency on the basis of the voltage Vi. The pulse output signal Vout is transferred to the gate of the transfer gate circuit TrN. When such an oscillation circuit is fabricated into an integrated circuit, the CR circuit 10 is externally attached to a single pad in an IC circuit 14.
In such an oscillation circuit, if the voltage Vi is equal to the voltage V.sub.SS ("0" level), the output voltage Vout of the gate circuit 12 is equal to the power source voltage V.sub.DD ("1" level) and then the transmission gate circuit TrN is turned on, that is, conductive. Accordingly, the power source voltage V.sub.DD is supplied to the CR circuit 10, so that the voltage Vi rises to "1" (V.sub.IH) level. The rise time of the voltage Vi is substantially proportional to the time constant of an onstate resistor of the transistor TrN and the capacitor Cx. While the voltage Vi is rising, at the instant that the voltage Vi exceeds the high level threshold voltage V.sub.IH in the Schmidt gate circuit 12, the output voltage Vout of the gate circuit 12 is inverted to change its logical state from "1" to "0". A load capacitance of the terminal from which the voltage Vi is derived is considerably larger than that of the terminal for the voltage Vout. The fall of the voltage Vout is sharper than the rise of the voltage Vi. Upon impression of the voltage Vout ("0" level), the transmission gate circuit TrN is nonconductive, so that the voltage Vi stops rising and at this instance falls according to the CxRx time constant of the CR circuit 10. As the voltage Vi falls below the low level threshold voltage V.sub.IL of the Schmidt gate circuit 12, the circuit 12 changes its logical state from "0" to "1". The rise, like the fall, is instantaneously produced. This operation repeats to produce a pulse signal at a predetermined frequency.
FIG. 2 shows another oscillation circuit made up of a p-channel MOS transistor as a transmission gate circuit TrP, a Schmidt gate circuit 16 operating in a positive-phase-sequence mode and a CR circuit 10. The gate circuit 16 produces inverted pulses of the pulses produced from the Schmidt gate circuit 12 shown in FIG. 1. The operation of this example is similar to that of the FIG. 1 circuit. No explanation of it will therefore be given.
FIG. 3 shows an actual arrangement of the oscillation circuit shown in FIG. 2. The IC circuit 14 uses a series connection of inverters 18, 20, 22, and 24 as the Schmidt gate circuit 12. A resistor R1 is inserted between the input terminal of the initial stage inverter 18 and the terminal for providing the voltage Vi from the CR circuit 10. Another resistor R2 is connected between the input terminal of the inverter 18 and the output terminal of the inverter 20. A divided volage Va produced according to a ratio of the resistances of the resistors R1 and R2 and a signal .phi. derived from the output terminal of the inverter 20 is applied to the input terminal of the initial stage inverter 18. The output signal .phi. produced from the inverter 20 is applied to the gate of the P-channel MOS transistor which allows the power V.sub.DD to be supplied to the CR circuit 10.
With such an oscillation circuit, it is assumed that the output signals from the inverters 18 and 20 are at "0" and "1" logic level, respectively. At the instant the voltages Vi and Va decrease and the voltage falls below the threshold voltage Vthl of the inverter 18, the output signals of the inverters 18 and 20 are inverted, as shown in FIG. 4B. At this instance, the voltage Vi has dropped to the low level threshold voltage V.sub.IL, as shown in FIG. 4A. The following relationship holds between the low level threshold voltage V.sub.IL and the threshold volage Vthl of the inverter 18 ##EQU1## wherein R1 and R2 are resistance of the resistors R1 and R2. The output signal .phi. of the inverter 20 is at the "0" level and the output signal Vout of the inverter 24 instantaneously changes its logical state from "1" to "0", so that the transmission gate circuit TrP is conductive. The gate circuit TrP allows the power V.sub.DD to pass to the CR circuit 10. Then the voltage Vi and Va starts to rise, as shown in FIGS. 4A and 4B. As the voltage Va reaches the threshold voltage Vthl of the inverter 18, as shown in FIG. 4B, the inverters 18 and 20 are inverted to change their output level from "1" to "0" and "0" to "1", respectively. The voltage Vi, at this time, has risen to the high level threshold voltage V.sub.IH, as shown in FIG. 4A. The following relationship holds between the high level threshold voltage V.sub.IH and the threshold voltage Vthl of the inverter 18 ##EQU2## The output signal Vout of the output stage inverter 24 changes instantaneously from "0" to "1" and the transmission gate circuit TrP becomes nonconductive. As a result, the gate circuit TrP stops the power supply to the CR circuit 10 and the voltage Vi starts to decrease. Such an operation repeats to generate the pulse signal Vout as shown in FIG. 4C from the output stage inverter 24.
Let us calculate the period T of the pulse signal Vout, or the periods T1 and T2 shown in FIG. 4C. The voltage Vi falls to the low level threshold voltage V.sub.IL and the output signals .phi. and Vout of the inverters 20 and 24 are inverted to the "0" level. At this time, the signal .phi. ("0" level) is transferred to the gate of the transmission gate circuit TrP which in turn is conductive, and the voltage Vi starts to rise. In this situation, an equivalent circuit, as shown in FIG. 6, is formed. More specifically, the switch SW is turned on corresponding to the inverting operation of the inverter 18. A current (il+i2), in response to the power source voltage V.sub.DD flows into the capacitor Cx and resistor Rx of CR circuit 10, and through the resistors R1 and R2, through an on-state resistor Rs of the transmission gate circuit TrP. Under this condition, the voltage V.sub.DD is mathematically expressed ##EQU3## where ##EQU4## in the equation the initial values are ##EQU5## From the equations (3) to (6), we see that i2(t) is ##EQU6## where ##EQU7## Since the voltage V.sub.IH is EQU V.sub.IH =Rf.multidot.i2(T1) (9)
then we readily see from the equations that the period T1 is ##EQU8## After the period T1, the voltage Vi rises to the high level threshold voltage V.sub.IH and the output signals .phi. and Vout of the inverters are at the "1" level. At this time the signal .phi. ("1" level) is transferred to the gate of the transmission gate circuit TrP which in turn is nonconductive. Then the voltage Vi starts to decrease. In this situation, an equivalent circuit as shown in FIG. 8 can be depicted. As shown, the switch SW is turned on the current (i3+i4) in response to the power source voltage V.sub.DD flows into the resistor Rx and the capacitor Cx of Cr circuit 10, through the resistors R1 and R2. When the current i3 flows into the resistor Rx and the current i4 flows into the capacitor Cx, the voltage V.sub.DD and the current (i3+i4) are expressed by the following equation: ##EQU9## In the equations, the initial values are ##EQU10## Accordingly, from the equations i3(t) is given ##EQU11## where ##EQU12## Since the voltage V.sub.IL is EQU V.sub.IL =Rx.multidot.i3(T2) (17)
we see from the equations (15) and (16) that the period T2 ##EQU13## Therefore, we have the period T of the pulse signal Vout from the equations (10) and (18) and we have the frequency given by ##EQU14## As seen from the above equations, the frequency f of the pulse signal depends on the power source voltage V.sub.DD and the voltages V.sub.IH and V.sub.IL. Further, the voltages V.sub.IH and V.sub.IL are dependent on the threshold voltage Vthl of the inverter 18, as seen from the equations (1) and (2). Therefore, when the voltage Vthl is proportional to a change in the voltage V.sub.DD, the frequency f is constant independent of the power source voltage V.sub.DD. In fact, however, the threshold voltage Vthl of the inverter 18 is not proportional to the change in the voltage V.sub.DD, since the on-state resistance of the P-channel or N-channel MOS transistor, making up the inverter, changes depending on the voltage V.sub.DD. Accordingly the voltage V.sub.IH and V.sub.IL are not proportional to the change in the voltage V.sub.DD. The resistors R1 and R2 are comprised of, for example, P-type diffusion resistors. For this reason, the resistors R1 and R2 tend to have a variation in the resistance values because of the nature of its manufacturing process. Further, since their resistances vary with voltages, the input impedance of the operational amplifier varies with a change in the voltage V.sub.DD. As described above, the frequency f of the pulse signal generated by the prior oscillation circuit changes unstably with variation in the power supply voltage V.sub.DD.